Skip to main content Skip to secondary navigation
Journal Article

Spatial: A Language and Compiler for Application Accelerators

Abstract

Industry is increasingly turning to reconfigurable architectures like FPGAs and CGRAs for improved performance and energy efficiency. Unfortunately, adoption of these architectures has been limited by their programming models. HDLs lack abstractions for productivity and are difficult to target from higher level languages. HLS tools are more productive, but offer an ad-hoc mix of software and hardware abstractions which make performance optimizations difficult. 

In this work, we describe a new domain-specific language and compiler called Spatial for higher level descriptions of application accelerators. We describe Spatial's hardware-centric abstractions for both programmer productivity and design performance, and summarize the compiler passes required to support these abstractions, including pipeline scheduling, automatic memory banking, and automated design tuning driven by active machine learning. We demonstrate the language's ability to target FPGAs and CGRAs from common source code. We show that applications written in Spatial are, on average, 42% shorter and achieve a mean speedup of 2.9x over SDAccel HLS when targeting a Xilinx UltraScale+ VU9P FPGA on an Amazon EC2 F1 instance.

Project page

A new Domain Specific Language for programming reconfigurable hardware from a parameterized, high level abstraction.
Author(s)
David Koeplinger
Matthew Feldman
Raghu Prabhakar
Yaqi Zhang
Stefan Hadjis
Ruben Fiszel
Tian Zhao
Luigi Nardi
Ardavan Pedram
Christos Kozyrakis
Kunle Olukotun
Journal Name
PLDI 2018: Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation
Publication Date
June, 2018
DOI
10.1145/3192366.3192379
Publisher
ACM